PhD: Design of High Speed and Energy Efficient Chip-to-Chip Transceivers

The University of Manchester - School of Computer Science

Supervisor: Dr Vasilis Pavlidis

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Application deadline: 15th November 2017

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Title: Design of High Speed and Energy Efficient Chip-to-Chip Transceivers

This research is FULLY funded (for UK and European students) and relates to a multi-partner European H2020 project in the area of High Performance Computing, which aims to unprecedentedly increase the computational power of today's high performance computers. This post offers, therefore, the opportunity to be part of this ambitious yet pragmatic research effort towards Exascale computing working with a diverse and enthusiastic team of software developers, computer architects, and chip designers.

The principal aim of the post is to develop a new interface type for chip-to-chip communication considering the stringent requirements of exascale systems requiring intra-node throughput of 10 Tb/s with energy consumption less than 1 pJ/bit. The strategy is to combine circuit design techniques with data encoding schemes to offer superior solutions that ultimately span more than one communication layer. This approach allows for more flexible energy, performance and reliability tradeoffs both at the physical and transport layers of the design abstraction, thereby exploring and exploiting a larger design space to further improve performance and energy efficiency. The successful candidate will develop and design a power efficient transceiver, investigating digital and beyond communication schemes over different types of media including silicon interposers and organic substrates. The proposed novel solutions will be incorporated in the high performance computing node developed within the EuroEXA project.

The successful candidate should have a BS or MSc qualification Electrical, Electronic, and/or Computer engineering and should meet the minimum entry requirements of the School. Expertise in analogue VLSI design and/or mixed signal circuit design and simulations is essential. Experience of Cadence/Synopsys EDA IC design tools and mixed signal circuit design flows are also highly desirable.

Interested candidates are encouraged to submit their applications using the on-line application system as soon as possible. Applications will be accepted until the position is filled and no later than November 15, 2017.

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