Researcher in FPGA/RTL Design for Optical Data Center Networks

About us

The optical networked systems team, part of Optical Networks Group at UCL, wishes to appoint up to 2 researchers at Research Fellow or Senior Research Fellow grade to work on EPSRC funded research projects that explores and develops optical networked system technologies for Cloud Data Centers and High Peformance Computing systems.

The scope of this project is to develop IP cores and a complete FPGA-based system to realise a network interface card (otherwise called Data Processing Unit) of an ultra-fast optical circuit switched network. The FPGA should perform MPI functions, parsing, processing, switching and forwarding data from/to memory/cache of embedded processor at high bitrates (>25 Gb/s/lane) to/from high-speed custom transceivers, offer closed-loop control to opto-electronic devices, implement control plane protocols and perform methods to support low-complexity burst-mode clock and data recovery.

About the role

The postholder(s) will lead the design and implementation of IP cores in Xilinx FPGAs to realise a range of network interface card functions needed to support future optical time division multiplexed optical networks. It will create parametirised, modular, high frequency logic blocks in SystemVerilog, HLS or other hardware description or higher description language suitable for FPGA programming. It will simulate using extensive testbenches, implement, test and validate across stressing onditions to access its overall performance.

Up to two posts at either Research Fellow (Grade 7: £42,099 - £50,585 per annum) or Senior Research Fellow (Grade 8: £51,474 - £60,521 per annum) level are available immediately and funded for 24 months in the first instance. Further funding to support the post may be available.

About you

Applicants should have a PhD in Electronic Engineering, Physics or related discipline (or about to submit a PhD thesis). Alternatively, they should have extensive FPGA programming and prototyping experience for networking applications. Knowledge of FPGA programming, ASIC design and fabrication and knowledge of network control and data plane operations are essential. Candidates should have strong programming skills in SystemVerilog, similar RTL language and/or HLS C/C++ and implementation on latest Xilinx FPGAs on networking functions. Significant experience in the design, implementation and verification of FPGA functions for optical network real-time data transport and control is also required.

To be appointed at the Senior Research Fellow level, candidates should have extensive post-doctoral experience in FPGA based optical networking or extensive FPGA engineering experience in developing network interface cards and switching technologies for high-speed networks. They should have a track record in world-leading scientific publications that have delivered impact (citations, invited talks, exploitation) as first author.

Further Details:

• To apply for the role, click the 'Apply’ button
• Applications close on 24th April at 23:59
• A job description and person specification can be accessed at the application link, as well as contact details for enquiries about the posts.

What we offer

As well as the exciting opportunities this role presents, we also offer some great benefits.

Visit https://www.ucl.ac.uk/work-at-ucl/rewards-and-benefits to find out more.

Our commitment to Equality, Diversity and Inclusion

We particularly encourage applications from candidates who are likely to be underrepresented in UCL’s workforce. These include people from Black, Asian and ethnic minority backgrounds; disabled people; LGBTQI+ people; and for our Grade 9 and 10 roles, women.

You can read more about our commitment to Equality, Diversity and Inclusion here : https://www.ucl.ac.uk/equality-diversity-inclusion/

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