| Qualification Type: | PhD |
|---|---|
| Location: | Coventry, University of Warwick, Warwick |
| Funding for: | UK Students |
| Funding amount: | £21,805 Please refer to advert |
| Hours: | Full Time |
| Placed On: | 21st April 2026 |
|---|---|
| Closes: | 15th June 2026 |
| Reference: | JY |
Research area and project description:
AI data centres are digital engines, yet ~30% of energy is wasted as heat in power conversion and distribution. Directly addressing the UK’s Clean Power 2030 and AI Infrastructure priorities, this PhD project pioneers fundamental technologies of Solid-State Transformers to enable highly efficient, reliable, and bi-directional energy flow control. You will develop next-generation power converters for mission-critical applications: from hyperscale AI hubs to MW-scale EV charging and smart grids.
The UK’s Modern Industrial Strategy and commitment to Net Zero demand a radical rethink of grid infrastructure, identifying Semiconductors and Clean Energy as national high-growth sectors. Traditional low-frequency power transformers are no longer fit for the high-dynamic requirements of renewable energy integration and the soaring power demands of AI workloads. Solid-state transformers (SSTs), powered by wide-bandgap (WBG) semiconductors and high-frequency transformers, are strategic enablers of this transition, providing enhanced grid flexibility, intelligent energy management, high efficiency, and a low footprint.
However, their widespread adoption remains constrained by reliability concerns. During high-power, high-frequency, and high-speed switching (high voltage and current slew rates), these advanced semiconductor chips and insulation materials endure extreme electro-thermal stress, leading to exacerbated electromagnetic interference and accelerated premature failure. As a result, first adopters have resorted to operating their devices conservatively. Substantial thermal and insulation margins are maintained, leaving the full potential of SSTs far from maximised and impeding the broader rollout of the technology.
This project focuses on the design, multi-physics characterisation, and optimisation of SSTs operating in the multi-kilovolt regime. Centred on the integration of WBG devices, the research will investigate the coupling mechanisms between electrical transients, localised thermal gradients, and mechanical strain. By leveraging state-of-the-art sensing and gate driving technologies, the candidate will experimentally explore complex switching behaviours and integrate these insights with high-fidelity, physics-based modelling to identify critical failure precursors. The goal is to propose innovative mitigation strategies – from active gate drive to structural optimisation – to enhance the ruggedness and efficiency of power converters for grid-scale and high-power-density applications.
The student will be supervised by Dr. Jiaqi Yan and Prof. Layi Alatise based at the University of Warwick, working within our world-class power electronics facilities. This project offers a unique opportunity to master the intersection of power semiconductor and high-voltage engineering, directly contributing to the UK's capability in next-generation energy infrastructure.
Scholarship:
The award will cover the UK tuition fee level, plus a tax-free stipend, currently £21,805, paid at the prevailing UKRI rate for 3.5 years of full-time study.
Eligibility:
Essential:
Desirable:
How to apply:
Interested candidates should submit a full formal application. Guidance and the application form are available via the above 'Apply' button.
Candidates must fulfil the University of Warwick entry criteria and obtain an unconditional offer before commencing enrolment. Should your application for admission be accepted, you should be aware that notification of acceptance for the PhD does not constitute an offer of financial support. Successful scholarship candidates will receive an official communication from the School of Engineering to confirm their award.
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